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NCP5201 Dual Output DDR Power Controller
The NCP5201 Dual DDR Power Controller is specifically designed as a total power solution for a high current DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of a linear regulator for the VTT memory termination voltage. The secondary regulator (VTT) is designed to automatically track at half the primary regulator voltage (VDDQ). An internal power good voltage monitor tracks both VDDQ and VTT outputs and notifies the user in the event of a fault on either output. Protective features include soft-start circuitry and undervoltage monitoring of VCC and VSTBY. The IC is packaged in a 5 x 6 QFN-18.
Features http://onsemi.com MARKING DIAGRAM
1 1 18-LEAD QFN, 5 x 6 mm MN SUFFIX CASE 505 NCP5201 AWLYYWW
* * * * * * * * * * *
Incorporates VDDQ, VTT Regulators Internal Switching Standby Regulator for VDDQ All External Power MOSFETs Are N-Channel Adjustable VDDQ VTT Tracks VDDQ/2 Fixed Switching Frequency of 250 kHz for VDDQ in Normal Mode Doubled Switching Frequency (500 kHz) for Standby Mode Soft-Start Protection for VDDQ Undervoltage Monitor Short-Circuit Protection for Both VDDQ and VTT Outputs Housed in a space saving 5 x 6 QFN-18
NCP5201 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week
PIN CONNECTIONS
Typical Applications
* DDR Termination Voltage * Active Termination Busses (SSTL-2, SSTL-3)
FBDDQ FBVTT PGND VSTBY VTT VTT OCDDQ VDDQ NC
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
SS COMP VCC TGDDQ BGDDQ SDDQ AGND S3_EN PWRGD
NOTE:
Pin 19 is the thermal pad on the bottom of the device.
ORDERING INFORMATION
Device NCP5201MN NCP5201MNR2 Package 18-Lead QFN* 18-Lead QFN* Shipping 61 Units/Rail 2500 Units/Reel
*5 x 6 mm For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
September, 2004 - Rev. 9
Publication Order Number: NCP5201/D
NCP5201
5V L1 1.0 mH
R2 10 k
R3 10 k
C1 1000 mF
5 VSTBY C4 1.0 mF
12 V C5 1.0 mF
C2 1.0 mF AGND
S3 4 11 S3_EN R6 16 W C10 100 nF R7 1.15 k C11 6.8 nF R12 20 k 8 VDDQ 1 C12 10 nF 17 18 C13 22 nF 12 7 C17 0.1 mF AGND RL1 62 k FBDDQ PWRGD TGDDQ SDDQ BGDDQ COMP VTT SS AGND OCDDQ VTT FBVTT PGND 15 13 14 5 6 2 3 VSTBY VCC 16 10
R8 4.7 W
S NTD60N02R D D NTD60N02R S L2 2.2 mH NTD60N02R COUT VTT (1000 mF x3) VDDQ
R1 4.7 W
R5 4.7 W
+
R10 1.1 k
+
C14 1000 mF
+
C15 470 mF
C15 1.0 mF
Figure 1. Application Diagram MAXIMUM RATINGS
Rating Power Supply Voltage (Pin 4) to PGND (Pin 3) and GND (Pin 12) Power Supply Voltage, VCC (Pin 16) to PGND (Pin 3) and GND (Pin 12) Gate Drive Voltage (Pins 14, 15) Input/Output Pins (Pins 1, 2, 5-11, 13, 17-18) Package Thermal Resistance Junction-to-Ambient Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol VSTBY VCC Vg VIO RqJA TJ TA Tstg MSL Value -0.3, 6.0 -0.3, 14 -0.3 DC, -4.0 for < 1.0 ms; 14 -0.3, 6.0 35 0 to +150 0 to +70 -55 to +150 2 Unit V V V V C/W C C C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC Standard JESD22-A114 except Pin 15 which is 1.5 kV. Machine Model (MM) 200 V per JEDEC Standard JESD22-A115 except Pin 14 which is 100 V. 2. Latchup Current Maximum Rating: 150 mA per JEDEC Standard JESD78.
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ELECTRICAL CHARACTERISTICS (VSTBY = 5.0 V, VCC = 12 V, TA = 0 to 70C, L2 = 1.7 mH, COUT = 3770 mF, COUT2 = 220 mF, RL1 = 100 kW, R7 = 1.0 kW, R10 = 1.0 k, R12 = 20 kW, R6 = 16 W, C12 = 3.0 nF, C11 = 6.0 nF, C10 = 80 nF, for min/max values unless otherwise noted)
Characteristic Supply Current S0 Mode Supply Current from VSTBY S3 Mode Supply Current from VSTBY S0 Mode Supply Current from VCC IST_S0 IST_S3 ICC_S0 S3_EN = LOW, VCC = 12 V S3_EN = HIGH, VCC = 0 V EN = HIGH, VCC = 12 V, 2.0 nF Capacitive Load to TGDDQ and BGDDQ - - - - - - 8.0 4.0 30 mA mA mA Symbol Test Conditions Min Typ Max Unit
Undervoltage Monitor VSTBY UVLO Lower Threshold Ratio of VSTBY UVLO Upper to Lower Threshold VCC UV Monitor Lower Threshold Ratio of VCC UV Monitor Upper to Lower Threshold VDDQ Switching Regulator FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current Oscillator Frequency in S0 Mode OCDDQ Pin Current Sink Minimum Duty Cycle Maximum Duty Cycle Soft-Start Timing VDDQ Standby Regulator FBDDQ Feedback Voltage, Control Loop in Regulation Load Regulation Peak Current Limit Peak Current Limit Blanking Time Oscillator Frequency in S3 Mode VDDQ Error Amplifier DC Gain Unity Gain Bandwidth Slew Rate VTT Active Terminator VTT Tracking VDDQ/2 at S0 Mode dVTT0 VDDQ/2 - VTT, IOUT = 1.8 A (Sink Current) IOUT = -1.8 A (Source Current) - - -30 - - - - - -2.3 2.3 - 30 - - mV mV A A GAIN Ft SR - COMP_GND = 200 nF, 1.0 W in series (Test circuit only) COMP_GND = 10 pF - - - 70 2.0 8.0 - - - dB MHz V/ms VFBQ LOADreg ILIMstbpk tbk Fstb TA = 25C TA = 0 to 70C ILOAD from 50 mA to 650 mA - - - 1.281 1.274 - - 400 - 1.300 - 0.4 2.0 - 500 1.319 1.326 - - - - V V % A ns kHz VFBQ Ifb F IOC Dmin Dmax tss1 CSS = 33 nF TA = 25C TA = 0 to 70C V(FBDDQ) = 1.3 V - V(OCDDQ) = 4.0 V - - 1.271 1.264 - 225 6.0 0 - 10 1.300 - - 250 10 - - 16 1.326 1.333 0.5 275 14 - 100 - V V mA kHz mA % % ms VSBUV- VSBUV+/ VSBUV- VCCUV- VCCUV+/ VCCUV- - - - - - - - - 4.25 1.05 9.23 1.14 - - - - V - V -
Source Current Limit Sink Current Limit
ILIMVTsrc ILIMVTsnk
3. Guaranteed by design, not tested in production.
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ELECTRICAL CHARACTERISTICS (VSTBY = 5.0 V, VCC = 12 V, TA = 0 to 70C, L2 = 1.7 mH, COUT = 3770 mF, COUT2 = 220 mF, RL1 = 100 kW, R7 = 1.0 kW, R10 = 1.0 k, R12 = 20 kW, R6 = 16 W, C12 = 3.0 nF, C11 = 6.0 nF, C10 = 80 nF, for min/max values unless otherwise noted)
Characteristic Control Section S3_EN Pin Threshold HIGH S3_EN Pin Threshold LOW S3_EN Pin Input Current PWRGD Pin ON Resistance PWRGD Pin OFF Current PWRGD LOW-to-HIGH Hold Time, For S3 to S0 or S5 to S0 Gate Drivers TGDDQ Gate Pull-HIGH Resistance TGDDQ Gate Pull-LOW Resistance BGDDQ Gate Pull-HIGH Resistance BGDDQ Gate Pull-LOW Resistance RH_TG RL_TG RH_BG RL_BG VCC = 12 V, V(TGDDQ) = 11 V VCC = 12 V, V(TGDDQ) = 1.0 V VCC = 12 V, V(BGDDQ) = 11 V VCC = 12 V, V(BGDDQ) = 1.0 V - - - - 3.0 2.5 3.0 1.3 - - - - W W W W S3_EN_H S3_EN_L IIN_EN PWRGD_R PWRGD_ LEAK thold - - - - - - 1.4 - - - - - - - - - - - - 0.5 0.5 80 1.0 200 V V mA W mA ms Symbol Test Conditions Min Typ Max Unit
PIN DESCRIPTION
N N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNN N N NNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN
1 2 3 4 FBDDQ FBVTT PGND VDDQ feedback pin for closed loop regulation. VTT regulator sense voltage. Power ground. VSTBY VTT 5 V Standby input voltage. VTT regulator output. 5, 6 7 8 9 OCDDQ VDDQ NC Overcurrent sense and program input for the VDDQ high-side FET. Reference input and power stage input for VTT regulator. Not connected. 10 11 PWRGD S3_EN AGND SDDQ Open drain status output. High impedance when the product is operating in S0 state and both DDQ and VTT regulators are in compliance. S3 mode enable input. High to enable. 12 13 14 15 16 17 18 19 Analog ground connection and remote ground sense. Inductor driven node and current limit sense input. BGDDQ TGDDQ VCC Gate driver output, VDDQ Low-Side N-Channel Power FET. Active during S0 mode. Gate driver output, VDDQ High-Side N-Channel Power FET. Active during S0 mode. 12 Volt input supply. This voltage is monitored by power good circuitry for mode selection. VDDQ error amplifier compensation node. Soft-start capacitor connection to ground. COMP SS TH_PAD Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC.
Pin No.
Symbol
Description
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VREF Voltage and Current Reference S3_EN 12 V VCC + - VREF VSTBY VSTBY 5 VST- UVLO + VSTGD - VREF PWRGD PGND 12 V OSC S0 S3 PGND SS PWM- COMP COMP VREF + - AMP A + - FBDDQ VDDQ VSTBY VTT Regulation Control SDDQ BGDDQ INREGVTT INREGDDQ ILIM OCDDQ 12 V- UVLO 12 VGD S0 Control Logic S3 VREFGD TSD Thermal Shutdown
+ -
IREF 12 V
TGDDQ VDDQ PWM Logic PGND VSTBY VSTBY
PGND
S0 S3
SC2PWR R R R + R GND - SC2GND + -
S3 S0 INREGDDQ INREGVTT
PGND VSTBY
VTT
PGND PGND FBVTT
AGND
PGND
Figure 2. Internal Block Diagram
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DETAILED OPERATION DESCRIPTIONS
General
The NCP5201 Dual DDR Power Controller combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of a linear regulator for the VTT memory termination voltage. VTT is designed to automatically track at half VDDQ. The inclusion of an internal PWM switching FET for VDDQ standby operation, both VDDQ and VTT power good voltage monitors, soft-start, undervoltage detection, and thermal shutdown, make this device a total power solution for high current DDR memory systems. The IC is packaged in 5 x 6 QFN-18.
IC Control States
The state decode logic and internal control functions are powered by 5 V VSTBY. An internal voltage reference and
Table 1. Control Logic State Truth Table
Input Conditions VSTGD Low High High High High High High S3_EN X Low Low High High High High 12 VGD X Low High High X Low X
bias current block is enabled when VSTBY exceeds 3.8 V. Once VREF reaches its regulation voltage, internal signal _VREFGD will be asserted HIGH. This transition wakes up the voltage monitor block, which in turn detects whether the VSTBY and VCC voltages are within certain preset regulation levels. If they are, the voltage monitor generates an internal HIGH VSTGD and 12 VGD respectively. There is an internal detection for 100% duty cycle of TGDDQ switching, if it occurs, an internal signal MAXDTY is asserted HIGH. The logic control block accepts an external signal at the S3_EN pin and internal voltage monitor signals MXDTY, 12 VGD and VSTGD to decode the operating states in accordance with Table 1. PWRGD is an open-drain logic output that signifies VDDQ and VTT are both in regulation in the S0 mode.
Operation Mode MAXDTY X X X Low High X X Prev. X X X S0 S0 S0 S3 Next S5 S5 S0 S0 S3 S3 S3
VDDQ Regulator in Normal (SO) mode
The VDDQ regulator in S0 mode is a switching synchronous rectification buck controller directly driving two external N-Channel power FETs. An external resistor divider sets the nominal output voltage. The control architecture is voltage mode fixed frequency PWM with external compensation, and with switching frequency fixed at 250 kHz 10%. As can be observed from Figure 1, the VDDQ output voltage is divided down and fed back to pin FBDDQ. This voltage connects to the inverting input of the internal error amplifier while the amplifier's noninverting input is connected to an internal voltage reference, VREF (= 1.3 V). The amplifier compares the feedback voltage to VREF and outputs an error signal to the PWM comparator. This error signal is compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse-width-modulated signal. This PWM signal drives the external N-Channel Power FETs via the TGDDQ and BGDDQ pins. External inductor L and COUT1 filter the output waveform, which is subsequently fed back to FBDDQ via a resistor voltage
divider to close the loop at VDDQ = VFBQ (1 + R2/R1). An adjustable soft-start is implemented, activated each time the IC exits state S5. When in normal mode, and regulation of VDDQ is detected, signal INREGDDQ will go HIGH to notify the Control Logic block.
Tolerance of VDDQ
The tolerance of VFBQ and the ratio of external resistor divider R7/R10 both impact the precision of VDDQ. With the control loop in regulation, VDDQ = (VFBQ)(1 + R7/R10). With a worst case (for all valid operating conditions) VFBQ tolerance of 2%, a worst case range of 2.5% for VDDQ will be assured if the ratio R7/R10 is specified as 0.9230 1%.
Synchronous Rectification
For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive nonoverlap timing control of the complementary gate drive output signals is provided to reduce large shoot-through currents, which degrade efficiency.
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VDDQ Regulator in Standby Mode (S3)
An internal P-Channel power FET switching at 500 kHz (doubled frequency), with peak current limit preset at 2.0 A, provides nonsynchronous switch-mode control while in the S3 state. In this mode, the internal P-Channel power FET derives its source from the 5 VSTBY pin. The 2.0 A peak current limit is designed to yield an average output current limit of 700 mA when using a 1.7 mH output inductor. When using this value inductor, the regulator will
Table 2. States, Operation and Output Pin Conditions
Operating Conditions Operation Mode S0 S3 S5 VDDQ Normal Standby H-Z VTT Normal H-Z H-Z
operate in discontinuous conduction mode (DCM) in the S3 state. And, switching in doubled frequency (500 kHz) is to reduce the peak conduction current. In this operating mode, the body diode of the external synchronous MOSFET acts as a flywheel diode and the MOSFET is never turned on. TGDDQ and BGDDQ are set Low to disable the external switches. Nominal output voltage and the PWM control scheme of Normal mode still apply.
Output Pin Conditions TGDDQ Normal Low Low BGDDQ Normal Low Low PWRGD H-Z Low Low
Fault Protection of VDDQ Regulator
During state S0, external resistor (RL1) sets current limit for the high-side switch. An internal 10 mA current sink at pin OCDDQ establishes the voltage drop across this resistor, which is compared to the voltage at the SDDQ pin when the high-side drive is high, and after a fixed period (500 ns) of blanking time to avoid false current limit triggering. When the voltage at SDDQ is lower than that at OCDDQ, an overcurrent condition occurs, both FETs are latched-off until the IC goes into S5 then S0, VDDQ will soft-start again. This protects against a short-to-ground condition on SDDQ or VDDQ. During state S3, the internal P-Channel power FET is activated and switching. If the conduction current of the FET is higher than 2.0 A after a fixed period (X500 ns) of blanking time, an overcurrent condition occurs, and the FET is turned off for the remainder of that switching cycle.
Feedback Compensation of VDDQ Regulator
will go HIGH to notify the control logic block. The input power path is from VDDQ. Gate drive power is derived from VSTBY. VTT is stable with any value of output capacitor greater than 220 mF, and is insensitive to ESR value ranging 2 mW to 400 mW.
VTT Active Terminator in Standby Mode (S3)
VTT output is high-impedance in S3 mode.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, bidirectional current limit is implemented, preset at 2.3 A magnitude.
Thermal Consideration of VTT Active Terminator
The compensation network is shown in Figure 1.
VTT Active Terminator in Normal Mode (S0)
The VTT terminator is designed to handle large transient output currents. If large currents are required for very long durations, then care should be taken to ensure the maximum junction temperature is not exceeded. The 5 x 6 QFN-18 has a thermal resistance 35C/W (dependent on air flow, grade of copper and number of VIAs).
Undervoltage Monitor
The VTT regulator is a two-quadrant linear regulator with internal N-channel power FETs to provide transient current sink and source capability up to 1.8 A. This output is activated in normal mode in state S0 when VDDQ is in regulation. It is in standby mode in state S3. When in normal mode and VTT is in regulation, signal INREGVTT
The IC monitors VSTBY and VCC. If VSTBY is higher than its preset threshold (derived from VREF, with hysteresis), _VSTGD is set HIGH. Operation is identical for VCC and _12 VGD. The CONTROL LOGIC accepts both _VSTGD and _12 VGD to determine the state of the IC.
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VSTBY
S3_EN
VCC
VDDQ tss1 Soft Start thold 200 ms VTT in H-Z thold 200 ms
VTT
PWRGD
Operating Mode S5 S0 S3 S0 S5
VSTGD goes HIGH
INREGVTT goes HIGH INREGDDQ goes HIGH, VTT is activated
12 VGD goes HIGH, VDDQ is activated
S3_EN goes HIGH, VTT goes into standby mode, then INREGVTT goes LOW, PWRGD goes LOW, then or VCC or 5 VCC goes LOW triggering VDDQ going into standby mode.
INREGVTT goes HIGH
VCC goes LOW; VDDQ is disabled, then INREGDDQ goes LOW, PWRGD goes LOW
S3_EN goes LOW, VDDQ is in normal mode, INREGDDQ goes HIGH, then VTT goes into normal mode
Figure 4. Power-Up and Power-Down Timing Diagram
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PACKAGE DIMENSIONS
18-LEAD QFN, 5 x 6 mm MN SUFFIX CASE 505-01 ISSUE B
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --- 0.45 0.65
PIN 1 LOCATION
E
2X
0.15 C
2X
0.15 C
TOP VIEW
0.10 C
18X
(A3) A
0.08 C SIDE VIEW
A1
C
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
D2
18X
L
e
1 9
18X
K
18 10 18X b
E2
0.10 C A B 0.05 C BOTTOM VIEW
NOTE 3
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NCP5201/D

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